In modern electronic devices, it is often necessary to transfer data between circuits in different digital clock domains. Although in many cases the clocks in the different domains are entirely unrelated, in some cases the clocks are generated from a common base clock or otherwise have a frequency relationship that may be used to time the transfer of information. For example, in at least one prior art memory system, a reference clock signal is used to generate both a memory clock 17 and a host clock 16. The memory clock 17 is used to time the transfer of data and commands to one or more memory devices via a high-speed, packet-oriented communication channel. The host clock 16 is used to manage memory access requests received from external agents and to format the requests into appropriate command and data packets for consumption in the memory clock 17 domain. To transfer a command or data packet to the memory clock 17 domain, control logic in the host clock 16 domain asserts the packet to logic in the memory clock 17 domain for as many cycles of the host clock 16 as required for the memory clock 17 domain to consume the packet.
One disadvantage of the above-described packet transfer technique is that, except for certain memory clock 17 to host clock 16 frequency ratios, the control logic in the host clock 16 domain will assert the packet to the memory clock 17 domain beyond the time necessary for the memory clock 17 domain to consume the packet. For example, suppose that the frequency between the memory clock 17 and the host clock 16 is such that the memory clock 17 domain can consume three-fourths of a packet during each cycle of the host clock 16. Because the memory clock 17 domain cannot consume an entire packet during a cycle of the host clock 16, the control logic in the host clock 16 domain outputs each packet for at least two cycle of the host clock 16, even though the memory clock 17 domain will consume the data in only one and one-third cycle of the host clock 16 (each quarter of the packet is consumed in a third of a cycle of the host clock 16). Consequently, each packet is asserted for two-thirds of a cycle of the host clock 16 longer than necessary, thereby reducing throughput and increasing response latency in the memory system.